Generally, dicing street is formed when a semiconductor device (chip) is fabricated on a wafer (such as a silicon wafer of a semiconductor wafer) in order to saw the semiconductor wafer during the final assembly and encapsulation/sealing phase. The cutting trails include widths from technology to technology, and the cutting trails surround each chip on the chip on each side (for example, four sides if the chip is rectangular). The incised trace is also referred to as a lineation or incision (kerf). Narrow available incisions or lines using conventional techniques include widths of approximately 62 m for example. Marking or notching limits the minimum distance between chips required by the cutting technique used and additionally accommodates a large number of structures used to control the manufacturing process. Such structures are typical process control monitoring test structures (PCM), lithographic alignment structures, wafer level reliability test circuits, film thickness and critical size (CD) measurement structures, and so on. When a cut operation is performed, the wafer estate (for example, silicon) on the wafer line is wasted and the said test structure is destroyed. The lineation or the width of the incision is determined by two factors.
(a) the width of the cutting blade;
(b) test and measure the width of the structure. The above test and measurement structures are no longer required after the cutting operation. Because these two factors mean the minimum width of a conventional incision, the area of the chip is smaller and the percentage of silicon or wafers that are wasted in the scribing is higher. Therefore, any reduction in the linewidth will increase the number of possible chips (CPW) per chip. This reduces the cost of the chip. The conventional method to reduce the lineation width is the repeated plasma dry etching method. However, the said repeated plasma dry etching method cannot be applied to copper-based, double ripple and metallized graphs, because copper cannot be etched by plasma. As a result, conventional methods use many as well as long over etching times, resulting in significantly reduced etching tool production due to the time required. However, there is no solution to dramatically reduce the linewidth for complex IC cases.
